1. Field of the Invention
The invention relates to a monitoring semiconductor device, a method for performing a deep n-typed well-correlated (hereinafter abbreviated as DNW-correlated) antenna rule check of an integrated circuit, and a semiconductor structure complying with the DNW-correlated antenna rule.
2. Description of the Prior Art
With rapid advancement of semiconductor fabricating technology, the integration level of integrated circuits (ICs) is bound to increase continuously in order to improve the device speed and performance. And the continuing shrinkage of the device dimensions, which in order to comply with current requirements for light weight, slimness, and compactness, involves a plurality of issues associated therewith, such as a thinner gate dielectric layer is required.
It therefore results another issue due to the thinner gate dielectric layer: The thinner gate dielectric layer, which overlies the channel region, is fragile and highly susceptible to damages from external sources during manufacturing processes. Should any damages caused to the gate dielectric layer, gate leakage current is inevitably increased, and it even causes device failure. In recent year, such damages to the gate dielectric layers are particularly found in the devices electrically connected to the deep n-typed well (hereinafter abbreviated as DNW), which is usually provided to prevent noise. Please refer to FIG. 1, which is a line graph illustrating a relationship between defected device ratio and DNW area ratio on a chip. In FIG. 1, the abscissa indicates the DNW area ratio on a chip, and the ordinate indicates the defected device ratio. As shown in FIG. 1, it is found that there is a linear relationship between the DNW area ratio and the defected device ratio. Consequently, it is concluded that such damage is getting worse when the DNW area ratio is increased.
Therefore, a device that is able to efficaciously monitor the abovementioned DNW-correlated defects is in need. Furthermore, a new rule, that is able to prevent the DNW-correlated defects, for the layout designer is also in need.